ElemRV-H (Hydrogen)¶
ElemRV-H is the entry-level platform of the Nonmetal class. It is designed for minimal area and simplicity: a single-issue in-order CPU, a shared BMB bus, no caches, and a small set of low-speed peripherals. All IO is routed through a pinmux controller, making the 12 physical pins fully reconfigurable in software.
Specifications¶
CPU |
VexiiRiscv RV32I_ifenciz, single-issue in-order, M-mode only |
Clock |
50 MHz system |
Interconnect |
BMB shared bus |
On-chip SRAM |
8 kB |
SPI Flash |
8 MB, Quad SPI XIP |
IO pins |
12 (via pinmux) |
Debug |
JTAG |
Memory Map¶
Region |
Base address |
Size |
Description |
|---|---|---|---|
SPI Flash (XIP) |
|
8 MB |
Code and read-only data |
On-chip SRAM |
|
8 kB |
Data, stack, and runtime code |
Peripherals |
|
– |
See peripheral map below |
Peripherals¶
Offsets are relative to the peripheral base address at 0xf0000000.
Peripheral |
Offset |
Size |
Description |
|---|---|---|---|
GPIO0 |
|
4 kB |
12-pin GPIO controller, all pins input capable - see GPIO |
I2C0 |
|
4 kB |
I2C controller with interrupt - see I2C Controller |
PIO0 |
|
4 kB |
Programmable IO, 3 pins - see Programmable IO |
PWM0 |
|
4 kB |
PWM controller, 2 channels - see Pulse-Width Modulation |
UART0 |
|
4 kB |
UART with full handshake (TX, RX, CTS, RTS) - see UART |
Pinmux |
|
4 kB |
Pin multiplexer for all 12 IO pins |
Interrupts¶
Source |
Description |
|---|---|
GPIO0 |
Triggered by configurable pin edge or level events |
I2C0 |
Triggered on transfer completion or error |
UART0 |
Triggered on receive, transmit, or error conditions |
Pinmux¶
Each physical pin can be assigned to one of two functions in software via the pinmux controller. The first function listed is the default.
Pin |
Function 0 |
Function 1 |
|---|---|---|
0 |
GPIO0_0 |
PWM0_0 |
1 |
GPIO0_1 |
PIO0_0 |
2 |
GPIO0_2 |
PIO0_1 |
3 |
GPIO0_3 |
PIO0_2 |
4 |
UART0_TX |
GPIO0_4 |
5 |
UART0_RX |
GPIO0_5 |
6 |
UART0_CTS |
GPIO0_6 |
7 |
UART0_RTS |
GPIO0_7 |
8 |
GPIO0_8 |
PWM0_1 |
9 |
GPIO0_9 |
I2C0_SCL |
10 |
GPIO0_10 |
I2C0_SDA |
11 |
GPIO0_11 |
I2C0_INT_0 |
Board Targets¶
ECPIX5¶
The ECPIX5 target maps ElemRV-H pins to the following board resources:
Pin |
ECPIX5 resource |
|---|---|
0 |
LED LD5 (blue) |
1 |
LED LD6 (red) |
2 |
LED LD7 (green) |
3 |
Button SW0 |
4 |
UART TX (UartStd) |
5 |
UART RX (UartStd) |
6 |
Pmod2 pin 0 |
7 |
Pmod2 pin 1 |
8 |
Pmod2 pin 2 |
9 |
Pmod2 pin 3 |
10 |
Pmod2 pin 4 |
11 |
Pmod2 pin 5 |
The SPI flash and JTAG are routed to Pmod6 and Pmod1 respectively.
IHP SG13G2¶
The SG13G2 target places IO pads around the chip perimeter:
Edge |
Position |
Signal |
|---|---|---|
South |
0 - 3 |
JTAG (TMS, TDI, TDO, TCK) |
South |
4 |
Reset |
South |
5 |
Clock |
East |
0 |
SPI CS |
East |
1 |
SPI SCK |
East |
2 - 5 |
SPI DQ0 - DQ3 |
West |
2 - 7 |
Pins 0 - 5 |
North |
2 - 7 |
Pins 6 - 11 |