Virtual Prototyping

Virtual prototyping runs an ElemRV platform without physical hardware. It is how you develop and debug software, and verify the RTL, long before an FPGA bitstream or a tape-out exists.

ElemRV offers three approaches that trade simulation accuracy for speed:

Approach	Tool	What runs	Use it for
RTL Simulation	Verilator	The full SoC as cycle-accurate RTL, with waveforms.	Verifying the hardware itself.
Emulation	Renode	Fast functional models of the CPU and peripherals (no RTL).	Rapid software bring-up and iteration.
Co-simulation	Renode + Verilator	Functional CPU plus the real peripheral RTL.	Running software against actual peripheral hardware, at near-emulation speed.

Pick emulation for the fast software loop, co-simulation to validate a driver against the real peripheral RTL while keeping that speed, and RTL simulation when you need full cycle accuracy and waveforms of the whole SoC.

All three are driven by Taskfile inside the container and select the platform with SOC and PDK (see Installation), for example:

task emulate SOC=ElemRV-H TARGET=SG13CMOS5L

• RTL Simulation
  • Running
  • Waveforms
  • When to use
• Emulation
  • Running
  • Console and I/O
  • When to use
• Co-simulation
  • Building
  • Running
  • When to use
  • Notes