Reset Controller

The Reset Controller manages multiple independent reset domains within a system. Each domain has a configurable assertion delay, ensuring downstream logic is held in reset for a minimum number of clock cycles before being released. The controller supports both software-triggered resets (via bus writes) and hardware-triggered resets (via external signals), with per-domain enable masking.

Features

• Configurable number of independent reset domains

• Per-domain assertion delay (minimum reset pulse width in clock cycles)

• Software-triggered reset via bus register write

• Hardware-triggered reset via external signal per domain

• Per-domain enable mask to suppress unwanted triggers

• Software acknowledge to clear pending software triggers

• Two implementations: ASIC (DummyResetController) and FPGA (GeneratorResetController)

Implementations

DummyResetController (ASIC)

Intended for ASIC designs. Takes explicit mainClock and mainReset inputs to build its own internal clock domain with synchronous, active-low reset. Both software triggers (via config.trigger) and hardware triggers (via io.trigger) are supported. The final reset output is ANDed with mainReset, so the external reset always overrides.

GeneratorResetController (FPGA)

Intended for FPGA designs. Uses a BOOT reset kind, relying on the FPGA fabric to handle the power-on reset automatically. Both software triggers (via config.trigger) and hardware triggers (via io.trigger) are supported. Hardware triggers are gated by the per-domain enable mask; software triggers are not. This results in logic suited to FPGA synthesis flows where the power-on reset is handled by the fabric itself.

Configuration

Available bus architectures:

• APB3

• TileLink

• Wishbone

By default, all buses are defined with 12 bit address and 32 bit data width.

ResetParameter defines a single reset domain.

ResetParameter

Name	Type	Description	Default
name	String	Identifier for this reset domain. Used to look up the domain by name.
delay	Int	Number of clock cycles the reset is held asserted after a trigger. Must be at least 1.

ResetControllerCtrl.Parameter configures the controller.

ResetControllerCtrl.Parameter

Name	Type	Description	Default
domains	List[ResetParameter]	List of reset domains. Must contain at least one entry.

Register Mapping

IP Identification:

The register map starts with an IP Identification block to provide all information about the underlying IP core to software drivers. This allows to provide backwards compatible drivers.

IP Identification Registers

Address	Bit	Field	Default	Permission	Description
0x000	31 - 24	API	0x0	Rx	API version of the implemented IP Identification.
	23 - 16	Length	0x8	Rx	Length of the IP Identification block in Bytes.
	15 - 0	ID	0xB	Rx	IP value of this IP core.
0x004	31 - 24	Major Version	0x1	Rx	Major number if this IP core. Version schema is major.minor.patch.
	23 - 16	Minor Version	0x0	Rx	Minor number if this IP core. Version schema is major.minor.patch.
	15 - 0	Patch Version	0x0	Rx	Patch number if this IP core. Version schema is major.minor.patch.

Reset Controller Registers

Address	Bit	Field	Default	Permission	Description
0x008	7 - 0	domains		Rx	Number of reset domains in this instance.
0x00C	N - 0	enable	all 1s	RW	Per-domain enable mask. When a bit is 0, hardware triggers for that domain are ignored. Software triggers via the trigger register are unaffected by this mask.
0x010	N - 0	trigger	0	RW	Software reset trigger. Writing a 1 to bit n asserts a reset on domain n. Bits are cleared by writing to the acknowledge register.
0x014	—	acknowledge	—	W	Write-only. Any write to this address clears all pending software trigger bits in the trigger register.